2D Heterostructures for Smaller Transistors

2D Heterostructures for Smaller Transistors

Author: Liam Critchley

Transistors are the fundamental building blocks of modern electronic devices. The most widely used transistors are MOSFETs (metal–oxide–semiconductor field-effect transistors), which can be miniaturized. Field-effect transistors, in general, are devices with three terminals: a source, a gate, and a drain. They control the flow of an electric current by the application of a voltage to the gate, which alters the conductivity between the source and the drain.

Scaling down MOSFETs further for ever smaller, more powerful devices runs into two key problems, however. The first is that the channel between source and drain cannot be shortened below a certain length without inducing adverse effects. The second is that the supply voltage cannot be reduced beyond a certain point. This means new types of transistors need to be developed. Impact-ionization MOSFETs, for example, can solve some of these problems, but have issues with stability that prevent their practical use.

Xiamou Wang, Feng Miao, Yi Shi and colleagues, Nanjing University, China, have fabricated impact-ionization transistors (IITs) using heterostructures composed of vertically stacked graphene, black phosphorus (BP), and indium selenide (InSe) sheets. The heterostructures were created by exfoliating the 2D materials from their bulk counterparts using sticky tape and depositing them on to a doped silicon substrate covered with an SiO2 layer. The materials were then stacked on top of each other using dry transfer methods.

The heterostructures multiply the number of charge carriers within the device during ballistic impact ionization processes. The transistors combine a small footprint and high stability with a low supply voltage. According to the researchers, the properties of their IITs could be further improved by optimizing the production process. This might allow their use in next-generation devices.


 

 

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